Many modern processors have multiple power states, which can be utilized to balance the needed performance of the processor against the power the processor consumes. When a processor is not executing code, it is idle. C-states are low power idle states defined by Advanced Configuration and Power Interface (APCI). Often used power states include C0, C1, C3, C6-C10. In the C6 power state, for example, the execution cores in the state save their architectural state before removing the core voltage. In the past, this state was saved to a C6 static random access memory (SRAM) that was places in a coherent fabric coupled to, but outside of, the processor.
Recently, there has been a desire to relocate the C6 SRAM into the core, instead of outside the core. In such a case, removing voltage to the core would cause the architectural state being stored in the C6 SRAM to be lost, which is not desirable.
Furthermore, if the architectural state is saved outside the core, such as in results to performing a flush operation to another memory, there wasn't a security issue in the past if other cores were also powered down and couldn't gain access to and potentially corrupt the saved state. However, if other cores remain powered, without protections in place, these cores may be able to access the stored architectural state. Such access could lead to obtaining valuable data or having the data be corrupted, which prevents the core from returning to its previous state when it returns from the low power state.